Digital Circuits and Systems
Undergraduate
Undergraduate
EEET 3047
Undergraduate
No
151940
4.5
No
School of Engineering
To assist students in developing the knowledge and skills to design combinational and sequential digital systems using modern electronic design flow, and to apply relevant design considerations and constraints
Integrated-Circuit Logic Families – TTL and CMOS. Combinational and arithmetic logic design – priority encoders, parity checkers, unsigned and signed binary adders, subtractors and multipliers; reducing delay using enhanced carry propagation techniques; timing specification and timing hazards. Design of synchronous and asynchronous digital circuits – set up and hold times, clock skew. State machine based design techniques – ASM chart, timing issues, data and control aspects of ASM design procedures. Digital system design with hardware description languages; programmable implementation technologies; electronic design automation flows; design considerations and constraints; design for test.
John F. Wakerly 2006, Digital Design: Principles and Practices, 4th edition, Prentice Hall, USA
Stephen Brown and Zvonko Vranesic 2009, Fundamentals of Digital Logic with VHDL Design, 3rd edition, McGraw Hill, USA
Common to all relevant programs | |
---|---|
Subject Area & Catalogue Number | Course Name |
EEET 1026 | Introduction to Computer Systems |
Nil
Component | Duration | ||
---|---|---|---|
INTERNAL, MAWSON LAKES | |||
Lecture | 2 hours x 13 weeks | ||
Tutorial | 1 hour x 13 weeks | ||
Practical | 2 hours x 13 weeks | ||
INTERNAL, OFFSHORE, KAPLAN HIGHER EDUCATION - SINGAPORE (INTENSIVE) | |||
Offshore (Lecture) | 4 hours x 5 days |
Note: These components may or may not be scheduled in every study period. Please refer to the timetable for further details.
Continuous assessment, e-portfolio, Examination, Practical
EFTSL*: 0.125
Commonwealth Supported program (Band 2)
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Fee-paying program for domestic and international students
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Non-award enrolment
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* Equivalent Full Time Study Load. Please note: all EFTSL values are published and calculated at ten decimal places. Values are displayed to three decimal places for ease of interpretation.