VLSI Design
Undergraduate
Undergraduate
EEET 4045
Undergraduate
No
013401
4.5
No
The 2025 timetable is
not yet available.
UniSA STEM
Course Alert: This course is no longer available for enrolment
To develop knowledge and skills in integrated circuit design and modelling using nanoscale CMOS technologies.
Evolution of CMOS technology and impact on society. Review of nMOS and pMOS transistor operations. CMOS process technology masks and design rules.
Static CMOS logic – dc and transient characteristics, noise margin, delay and power. Device sizing versus performance.
Designing CMOS logic circuits – traditional versus pass transistor and pass gate logic, impact on device count (circuit area) and output logic levels.
Delay modelling of single stage and multistage circuits – effort delay (logical effort and electrical effort), parasitic delay and path delay. Delay minimisation in multistage circuits.
Interconnects – signal integrity and delay, interconnect modelling.
Pseudo NMOS, static CMOS, dynamic CMOS and domino CMOS logic families.
Sequential CMOS circuits – clocking strategies, non-overlapping clocks.
Static CMOS RAM – Read/Write stability, sense amplifier.
CMOS datapaths and arithmetic circuits
Custom CMOS integrated circuit design using nanometre technologies, modelling and analysis techniques using modern tools.
Weste, N & Harris, D. 2011, CMOS VLSI Design: A Circuits and Systems Perspective, 4th , Pearson Education, Boston
Weste, N & Harris, D. 2011, Integrated Circuit Design, 4th, Pearson, Boston
Common to all relevant programs | |
---|---|
Subject Area & Catalogue Number | Course Name |
EEET 2018 | Analogue Devices and Circuits |
Nil
Component | Duration | ||
---|---|---|---|
INTERNAL, MAWSON LAKES | |||
Lecture | 2 hours x 13 weeks | ||
Computer Practical | 2 hours x 13 weeks | ||
Tutorial | 1 hour x 12 weeks |
Note: These components may or may not be scheduled in every study period. Please refer to the timetable for further details.
Practical, Report, Test
EFTSL*: 0.125
Commonwealth Supported program (Band 2)
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Fee-paying program for domestic and international students
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Non-award enrolment
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* Equivalent Full Time Study Load. Please note: all EFTSL values are published and calculated at ten decimal places. Values are displayed to three decimal places for ease of interpretation.