VLSI Design

Course aim

To assist students in developing the knowledge and practice-based skills to design Very Large Scale Integrated (VLSI) circuits and systems using modern nanoscale CMOS technologies.

Course content

VLSI technology trend: modern nanometer CMOS technologies – performance, impact and challenges; typical CMOS process technology masks and design rules; modelling and analysis of integrated circuits using SPICE – MOS model parameters; NMOS and CMOS logic families; static CMOS logic design: inverter example – device sizing, inversion voltage, noise margin, delay and power; design and analysis of combinational and sequential CMOS building blocks: performance issues and optimisation techniques; interconnects and process variability; cell-based system design: floor planning; datapaths; design for testability; modern computer aided design (CAD) tools to design and analyse custom CMOS integrated circuits.

Textbook(s)

Weste, N & Harris, D. 2011, Integrated Circuit Design, 4, Pearson, Boston

Prerequisite(s)

Nil

Corequisite(s)

Nil

Teaching method

Component	Duration
INTERNAL, MAWSON LAKES
Lecture	2 hours x 13 weeks
Computer Practical	2 hours x 13 weeks
INTERNAL, OFFSHORE, KAPLAN HIGHER EDUCATION - SINGAPORE (INTENSIVE)
Offshore	20 hours x 1 week

Note: These components may or may not be scheduled in every study period. Please refer to the timetable for further details.

Assessment

Class tests, Examination, Practical projects

Fees

EFTSL*: 0.125
Commonwealth Supported program (Band 2)
To determine the fee for this course as part of a Commonwealth Supported program, go to:
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Fee-paying program for domestic and international students
International students and students undertaking this course as part of a postgraduate fee paying program must refer to the relevant program home page to determine the cost for undertaking this course.

Non-award enrolment
Non-award tuition fees are set by the university. To determine the cost of this course, go to:
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Not all courses are available on all of the above bases, and students must check to ensure that they are permitted to enrol in a particular course.

* Equivalent Full Time Study Load. Please note: all EFTSL values are published and calculated at ten decimal places. Values are displayed to three decimal places for ease of interpretation.